Smart Monte Carlo for Yield Estimation

We propose techniques for accurate and computationally viable estimation of timing yield using circuit-level Monte Carlo simulation. Our techniques are based on well-known variance reduction approaches from Monte Carlo simulation literature. By adapting these techniques to the yield estimation problem, one can reduce the number of Monte Carlo samples required in order to estimate yield within a desired accuracy. As a result, the same accuracy can be obtained with much fewer circuit-level simulations. The variance reduction techniques we use require a cheap approximation to circuit delay to guide the choice of Monte Carlo samples. For this purpose, we use the logical effort approximation to compute path delays. Most yield estimation approaches require approximate gate delay models and approximate methods for probability density function propagation. Monte Carlo estimation of timing yield does not suffer from the inaccuracies involved in these approximations but is generally considered to be too expensive computationally. The use of variance reduction techniques has the potential to make Monte Carlo simulation a computationally viable as well as accurate method for yield estimation.